View CY7C147-45DMB_1092058.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

7c147: 12/4/89 Revision: Thursday, November 11, 1993
Features
D
D D D D D D
Automatic power down when dese lected CMOS for optimum speed/power High speed 25 ns Low active power 440 mW (commercial) 605 mW (military) Low standby power 55 mW TTL compatible inputs and outputs
Capable of withstanding greater than 2001V electrostatic discharge
The CY7C147 is a high performance CMOS static RAMs organized as 4096 words by 1 bit. Easy memory expansion is provided by an active LOW chip enable (CE) and three state drivers. The CY7C147 has an automatic power down feature, reducing the power consumption by 80% when deselected . Writingtothedeviceisaccomplishedwhen the chip select (CE) and write enable
Functional Description
(WE) inputs are both LOW. Data on the input pin (DI) is written into the memory location specified on the address pins (A0 through A11). Readingthedeviceisaccomplished bytak ingthechipenable(CE)LOWwhile(WE) remains HIGH. Under these conditions, the contents of the location specified on the address pins will appear on the data output (DO) pin. The output pin remains in a high impe dance state when chip enable is HIGH, or write enable (WE) is LOW.
Pin Configuration
4K x 1 Static RAM
CY7C147
Logic Block Diagram
DIP Top View
DI
A0 A1 INPUT BUFFER A2 A3 A4 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VCC A6 A7 A8 A9 A10 A11 DI CE
SENSE AMP
A1 A2 A3 A6 A7
ROW DECODER
A0
A5 DO
64 x 64 ARRAY
DO
WE GND
C147 2
CE
COLUMN DECODER POWER DOWN
WE
A4
A5 A8 A A 9 10 A11
C147 1
Selection Guide
Maximum Access Time (ns)) (
Commercial Military Maximum Operating Current (mA)) Commercial pg ( Military Maximum Standby Current (mA)) Commercial y ( Military
Cypress Semiconductor Corporation
7C147-25
25 90 15
7C147-35
35 35 80 110 10 10
7C147-45
45 45 80 110 10 10
D
3901 North First Street
D
San Jose D CA 95134 D 408-943-2600 December 1985 - Revised November 1992
7c147: 12/4/89 Revision: Thursday, November 11, 1993
CY7C147
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature . . . . . . . . . . . . . . . . . . -65_C to +150_C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . -55_C to +125_C Supply Voltage to Ground Potential (Pin 18 to Pin 9) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . -3.0V to +7.0V
Electrical Characteristics
Output Current into Outputs (LOW) . . . . . . . . . . . . . . 20 mA Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . >2001V (per MIL STD 883, Method 3015) Latch Up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . >200 mA
Operating Range
Ambient Range Temperature VCC
Commercial Military[1]
0_C to +70_C -55_C to +125_C
5V 10% 5V 10%
Over the Operating Range[2]
7C147-25 7C147-35, 45 Min. Max. Unit Test Conditions Min. Max.
Parameter
Description
VOH VOL VIH VIL IIX IOZ IOS ICC ISB
Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating p g Supply Current S lC t Automatic CE[4] Power Down Current P D C t
VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 12.0 mA
2.4 0.4 2.0 -3.0 6.0 0.8 +10 +50 -350 90 15
2.4 0.4 2.0 -3.0 -10 -50 6.0 0.8 +10 +50 -350 80 110 10 10
V V V V
GND < VI < VCC GND < VO < VCC Output Disabled VCC = Max., VOUT = GND VCC = Max., , IOUT = 0 mA A Max. VCC, CE > VIH Com'l Mil Com'l Mil
-10 -50
mA mA
mA mA mA
[5] Capacitance
Parameter Description Test Conditions Max. Unit
CIN COUT
Notes:
Input Capacitance Output Capacitance
TA = 25_C, f = 1 MHz, 25 C, 5 VCC = 5.0V
4. 5.
8 8
pF pF
1. 2. 3.
TA is the "instant on" case temperature. See the last page of this specification for Group A subgroup testing information. Duration of the short circuit should not exceed 30 seconds.
A pull up resistor to VCC on the CE input is required to keep the de vice deselected during VCC power up, otherwise ISB will exceed values given. Tested initially and after any design or process changes that may af fect these parameters.
2
7c147: 12/4/89 Revision: Thursday, November 11, 1993
CY7C147
AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to:
R1 329W
5V OUTPUT 5 pF INCLUDING JIG AND SCOPE
R1 329W 3.0V R2 255W
(b)
R2 255W
(a)
GND < 5 ns
ALL INPUT PULSES 90% 90% 10% 10% < 5 ns
C147 4
C147 3
THEVENIN EQUIVALENT 125W OUTPUT
1.90V
7C147-25 7C147-35 Min. Max. 7C147-45 Min. Max. Unit
Switching Characteristics Over the Operating Range[6]
Parameter READ CYCLE
tRC tAA tOHA tACE tLZCE tHZCE tPU tPD Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid CE LOW to Low Z
[7] [7, 8]
Description
Min.
Max.
25 25 3 25 5 20 0 20
35 35 5 35 5 30 0 20
45 45 5 45 5 30 0 20
ns ns ns ns ns ns ns ns
CE HIGH to High Z
CE LOW to Power Up CE HIGH to Power Down
WRITE CYCLE[9]
tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Write Cycle Time CE LOW to Write End Address Set Up to Write End Address Hold from Write End Address Set Up to Write Start WE Pulse Width Data Set Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[7]
25 25 25 0 0 15 15 0 0 15
9.
35 35 35 0 0 20 20 10 0 20
45 45 45 0 0 25 25 10 0 25
ns ns ns ns ns ns ns ns ns ns
[7, 8]
Notes: 6. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V input pulse levels of 0 to 3.0V and output , , loading of the specified IOL/IOH and 30 pF load capacitance.
7. 8. At any given temperature and voltage condition, tHZ is less than tLZ for all devices. tHZCE and tHZWE are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady state voltage.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data in put set up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3
7c147: 12/4/89 Revision: Thursday, November 11, 1993
CY7C147
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC ADDRESS DATA OUT
Read Cycle No. 2[10, 12]
tOHA PREVIOUS DATA VALID
tAA DATA VALID
C147 5
CE tLZCE HIGH IMPEDANCE tPU 50% tACE
tRC tHZCE DATA VALID tPD 50%
DATA OUT VCC SUPPLY CURRENT
HIGH IMPEDANCE ICC ISB
C147 6
Write Cycle No. 1 (WE Controlled)[9]
tWC ADDRESS tSCE CE tSA WE DATA IN DATA OUT
Notes:
10. 11. WE is HIGH for read cycle. Device is continuously selected, CE = VIL. 12. Address valid prior to or coincident with CE transition LOW .
tAW
tPWE tSD DATAIN VALID tHZWE tHD
tHA
DATA UNDEFINED
tLZWE HIGH IMPEDANCE
C147 7
4
7c147: 12/4/89 Revision: Thursday, November 11, 1993
CY7C147
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[9, 13]
tWC ADDRESS tSA CE tAW tPWE WE tHA tSCE
tSD DATA IN tHZWE DATAIN VALID
tHD
HIGH IMPEDANCE DATA OUT DATA UNDEFINED
C147 8
Notes: 13. If CE goes HIGH simultaneously with WE HIGH, the output re mains in a high impedance state.
Typical DC and AC Characteristics
OUTPUT SOURCE CURRENT (mA)
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE
1.4
SB SB
NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE
1.2 1.0 0.8 ICC
OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE
120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC = 5.0V TA = 25_C
NORMALIZED I CC, I
1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5
ICC
VIN = 5.0V TA = 25_C
NORMALIZED I CC, I
1.2
0.6 0.4 0.2
VCC = 5.0V VIN = 5.0V ISB 25 125
ISB 5.0 5.5 6.0 0.0 -55
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (_C)
OUTPUT VOLTAGE (V)
NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE
1.4 1.3 1.2 1.1 TA = 25_C 1.0 1.6
NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT (mA) 160 140 120 100 80 60 40 20 0 25 125
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE
NORMALIZED tAA
NORMALIZED tAA
1.4
1.2
1.0 VCC = 5.0V 0.8
VCC = 5.0V TA = 25_C
0.9 0.8 4.0
4.5
5.0
5.5
6.0
0.6 -55
0.0
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (_C)
OUTPUT VOLTAGE (V)
5
7c147: 12/4/89 Revision: Thursday, November 11, 1993
CY7C147
Typical DC and AC Characteristics
TYPICAL POWER ON CURRENT vs. SUPPLY VOLTAGE (7C148)
3.0 2.5 TA = 25_C 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 ISB 1K 30.0 25.0 20.0 15.0 10.0 5.0 0.0
(continued)
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING
1.4 1.3 1.2 1.1 1.0 0.9 0.8 0 200 400 600 800 1000 0 10 20 30 40 50 VCC = 5.0V TA = 25_C VIN = 0.5V
NORMALIZED ICC vs. CYCLE TIME
DELTA t
RESISTOR TO VCC
AA
W CS PULL UP
VCC = 4.5V TA = 25_C
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
NORMALIZED I CC
NORMALIZED I PO
(ns)
CYCLE FREQUENCY (MHz)
Ordering Information
Speed (ns) Ordering Code Package Name Package Type Operating Range
25 35 45
CY7C147-25PC CY7C147-35PC CY7C147-35DMB CY7C147-45PC CY7C147-45DMB
P3 P3 D4 P3 D4
18 Lead(300 Mil)MoldedDIP 18 Lead(300 Mil)MoldedDIP 18 Lead (300 Mil) CerDIP 18 Lead(300 Mil)MoldedDIP 18 Lead (300 Mil) CerDIP
Commercial Commercial Military Commercial Military
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameters Subgroups
Switching Characteristics
Parameters Subgroups
VOH VOL VIH VIL Max. IIX IOZ ICC ISB
1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3
READ CYCLE
tRC tAA tOHA tACE
WRITE CYCLE
7,8,9,10,11 7,8,9,10,11 7,8,9,10,11 7,8,9,10,11
tWC 7,8,9,10,11 tSCE 7,8,9,10,11 tAW 7,8,9,10,11 tHA 7,8,9,10,11 tSA 7,8,9,10,11 tPWE 7,8,9,10,11 tSD 7,8,9,10,11 tHD 7,8,9,10,11 Document #: 38 00030 D
6
7c147: 12/4/89 Revision: Thursday, November 11, 1993
CY7C147
Package Diagrams
18 Lead (300 Mil) CerDIP D4
MIL-STD-1835 D-8 Config. A
18 Lead (300 Mil) Molded DIP P3
E
Cypress Semiconductor Corporation, 1992. The information contained herein is subject to change without notice.
Cypress Semiconductor Corporatio n assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress Semiconductor Corporation product. Nor does it convey or imply any license under pa tent or other rights. Cypress Semicon ductor does not authorize its products for use as critical components in life support systems where a malfunction or failure of the product may reason ably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life support systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies Cypress Semiconductor against all damages.
7

▲Up To Search▲

Price & Availability of CY7C147-45DMB

	To Download CY7C147-45DMB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .